Job description
Job Requirements: Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools. Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must. Expertise in floor planning including power grid design to meet EMIR specifications. Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix…