Job description
Job Description: Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL. Translate architectural specifications into synthesizable RTL code. Perform RTL simulations and debug logic issues. Collaborate with verification engineers to develop and review test plans and coverage. Support synthesis, timing analysis, and logic equivalence checks (LEC). Interface with physical design and DFT teams to ensure design feasibility and testability. Optimize designs for per…