Job description
Responsibilities 5 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. Strong knowledge of UVM, advance UVM, System Verilog. Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM. Understanding of complete functional verification cycle will be added advantage. Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required. Ski…