Job description
Design Verification (DV) – Job Description Experience Range: 3 to 15 Years Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune Role Overview The Design Verification (DV) Engineer is responsible for ensuring functional correctness, performance, and reliability of ASIC and SoC designs using coverage-driven verification methodologies. The role spans IP, subsystem, and full-chip verification using SystemVerilog/UVM, assertion-based verification, protocol verification, and pow…