Job description
Position Description: Design Verification role for IP development team. B. Tech/M.Tech with 10 years of relevant experience. Position is based in Bangalore/Noida, part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs. In addition to UVM functional verification, role could involve Formal verif…