Job description
Role: VHDL/FPGA Design Engineer Location :Hyderabad Job responsibilities: Designing High Performance digital blocks for Complex Communication Coding using VHDL. Hands-on with RTL development (VHDL), simulation, writing test benches, and debug. Experience with developing timing constraints and running state-of-the-art synthesis tools, timing analysis tools, such as Xilinx Vivado suite. Participate in module architecture and specification. Block level design verification Strong hands-…