Job description
RTL FPGA Design Engineer Experience: 2 to 4 Years Location: Hyderabad, India. Job Description: Minimum of 2 years of RTL design and development experience, preferably in a customer facing role Minimum of 2 years of experience in FPGA Verilog design, technology, and tools Experience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc. Proficient in debugging RTL code using simulation tools Excellent ability to analyze and is…