Job description
Support execution of physical design flow for SoC projects under guidance from senior engineers Assist in Place and Route (PnR) activities to help optimize chip layout, performance, and power Participate in basic sign-off checks including Design Rule Check (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA) Learn and use EDA tools such as Genus, Innovus, Quantus, and RedHawk for design implementation and analysis Support development of simple TCL and Perl scripts to automate …