Job description
Description As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state‑of‑the‑art verification methodologies in ever‑increasing design complexities, from UVM, C/C++ co‑simulation, system emulation to mixed‑mode simulation & formal verification. The goal is simple – to achieve zero‑defects with the best and smartest approach to the large verification space. Requirements Experience in UVM verificatio…